1. Field of the Invention
The present invention relates to an input/output control system (herein abbreviated as IOC) which controls transmission of data communicated between a central control unit (below, abbreviated as CC) and an input/output unit (herein abbreviated as IO). More particularly, it relates to an IOC capable of a high operation speed and having a high reliability.
2. Description of the Related Art
The IOC 10 operates to control an IO 12, such as a typewriter, magnetic tape apparatus, magnetic disk apparatus, and so on. Recently, the IO has come under the control of a microprogram. In general , the processors operated by such a microprogram control are classified into two types: (i) a bit-slice processor, and (ii) a one-chip processor
The bit-slice processor (i) has a high processing speed, on the order of nanoseconds, and a high processing capability, and thus the bit-slice processor is frequently used for a high speed IOC. In the bit-slice processor, however, a special microprogram is necessary, and therefore, the processor has disadvantages in that it is not beneficial from the viewpoint of a general-purpose applicability in firmware, and that design of relevant hardware and firmware is difficult.
The one-chip processor (ii) does not, however, have the disadvantages inherent to the bit-slice processor (i), and therefore the one-chip processor can be utilized over a wider practical range, compared with the bit-slice processor. The one-chip processor does, however, have a disadvantage in that the processing speed, on the order of nanoseconds, of the one-chip processor is lower than that of the bit-slice processor. The IOC to which the present invention is adapted is controlled with the one-chip processor.
The prior art IOC has two major features, as explained hereinafter. First, a direct memory access (so called DMA) transfer is realized by a microprogram, and second, an interruption to a microprocessor (.mu.P) 14 takes place every time a program mode (PM) operation is initiated during a DMA transfer.
In view of the above-mentioned two features, two problems arise in the prior art IOC. First, a data transmission rate is lowered, and accordingly, a high speed IOC cannot be expected, and second, the related firmware is very complicated. An example of such a prior art IOC is shown in U.S. Pat. No. 4,467,454.